Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

Desynchronization: an easy approach to Asynchronous design
 
    In the pages proceeding, we will try to explain some thundamentals princliples of the desynchronization model, such as non-overlaping and overlaping designing methods. In addition to that, some basic properties of asynchronous circuits will be presented in order for the reader to understand easier our attemps of desynchronization. For more information, please read the following references:
  1. J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou. A Concurrent Model for De-synchronization. In Handouts of the International Workshop on Logic Synthesis, pages 294-301, 2003. (pdf)
  2. I. Blunno, J. Cortadella, A. Kondratyev, K. Lwin and C. Sotiriou. Handshake Protocols for De-synchronization. In  Proceedings of the 10th International Synposium on Asynchronous Circuits and Systems, April 2004.   (pdf) 
An HTML version of the first paper can be found here...

To read more about the principles of de-synchronization (parts of first paper) follow the clickable images below:

                      Basics of DesynchronizationNon-Overlapping DesignOverlapping Design



General De-synchronization models

\begin{figure}\centerline{\psfig{figure=Fig/timing_new3.eps,width=0.6\linewidth}}\vspace*{-4.5mm} \end{figure}
Timed Model


                                          Flow-equivalence       Marked Graph Representation of De-synchronization model for a linear pipeline and a ring



                                                                                                Classification of the asynchronous protocols

For more information on the implementation of the model click here...

 

 


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Last revision date: 04 Oct, 2005 by webmaster@ics.forth.gr

Last Content revision date: 04 Oct, 2005 by Asynchronous Circuits and Systems Group.
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