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 Computer Architecture and VLSI Systems Laboratory

Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

De-synchronization Basics
 
  

The de-synchronization approach presented in this section aims at the substitution of the global clock of a circuit by a set of asynchronous controllers that guarantee an equivalent behavior. The method assumes that the circuit has combinational blocks (CL) and registers implemented with D flip-flops (FF), all of them working with the same clock edge (e.g. rising in Figure 1(a)).

Figure 1: Synchronous and de-synchronized circuit.
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The de-synchronization method proceeds in three steps:

  1. Conversion of the flip-flop-based synchronous circuit into a latch-based one (M and S latches in Figure 1(b)) by: decoupling local clocks for master and slave latches and (optionally) improving performance through retiming, i.e. by moving latches across combinational logic.
  2. Generation of matched delays for combinational logic (denoted by rounded rectangles in Figure 1(b)). Each matched delay must be greater than the delay of the critical path of the corresponding combinational block.
  3. Interconnection of controllers for local clocks.

Figure 2 depicts a synchronous netlist after conversion into latch-based design, possibly after applying the retiming mentioned above. The shadowed boxes represent latches, whereas the white boxes represent combinational logic. Latches must alternate their phases. Latches with a label 0 (1) at the clock input represent the even (odd) latches, transparent when the clock is low (high). Data transfers must always occur from even (master) to odd (slave) latches and vice-versa.

Figure 2: Synchronous circuit with a global clock.
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Initially, only the latches corresponding to one of the phases store valid data. Without loss of generality, we will assume that these are the even latches. The odd latches store bubbles, in the argot of asynchronous circuits.