Heraklion, Greece - August 3, 2023 - Researchers of the Computer Architecture and VLSI Systems (CARV) Laboratory of the Institute of Computer Science (ICS), FORTH, announced today the availability of K3s, a lightweight Kubernetes distribution, for processors based on the RISC-V architecture. This achievement marks a significant milestone for the RISC-V community, as it is expected to foster innovation and collaboration among developers, researchers, and industry partners who are interested in exploring the potential of RISC-V for cloud computing.
Kubernetes is the leading open-source container orchestration platform, widely used by leading cloud providers, organizations, and enterprises around the world. Its widespread adoption has been instrumental in driving the cloud-native computing movement, empowering organizations to leverage infrastructure from the cloud to the edge to its fullest potential. K3s, a Cloud Native Computing Foundation (CNCF) project, is a certified Kubernetes distribution optimized for resource-constrained devices, such as the experimental boards currently available for RISC-V.
RISC-V, an open instruction set architecture, has been gaining momentum as a powerful and versatile alternative in the world of computer processors. FORTH has an ongoing commitment to support and contribute to the RISC-V hardware and software ecosystems, being a member of the RISC-V Foundation and collaborating with partners across Europe in several research and development projects that use RISC-V technology.
Making K3s available for RISC-V involved adapting both K3s and its software dependencies to the RISC-V instruction set. The effort has produced RISC-V porting contributions to over 10 related software projects (including runc, CoreDNS, Helm, and Traefik), most of which have already been merged into the official codebases. We expect this number to continue to grow, as higher-level services and applications are being ported to the new platform. All necessary changes have been shared with the community.
Kubernetes on RISC-V is one of the outcomes of the RISER project (GA no. 101092993), which develops the first all-European RISC-V cloud server infrastructure, including a microserver board integrating up to four RISC-V chips, high-speed storage, and networking. RISER brings together 7 partners from industry and academia to jointly develop and validate open-source designs for standardized form-factor system platforms, suitable for supporting cloud services. This work has also been funded by the REBECCA project (GA no. 101097224), which aims to develop an efficient and secure edge-AI system based on an open RISC-V processor. REBECCA is powered by a consortium of 24 partners that will create a complete hardware and software stack incorporating beyond-state-of-the-art technologies in the areas of processing units, hardware accelerators, reconfigurable hardware, as well as AI libraries and frameworks.
For more information, please visit www.riser-project.eu and https://www.rebecca-chip.eu.
