Simultaneous Multithreading Processors (SMT) are dominating the processor server market. Their main advantages are that SMT cores improve resource utilization and throughput over single-threaded processors, thus reducing the processor count in data centers and, thus, system costs. SMT is the only multithreading paradigm that allows the issue of instructions from multiple threads in the same cycle. In other words, allowing multiple threads to compete for intra-core resources like functional units or caches introduces intra-core interference. Because of the inter-thread intra-core interference, the execution time of the co-running applications sharing the thread becomes unpredictable; their execution time strongly depends on the application it is co-running to.
This talk will focus on strategies to reduce the intra-core interference and improve the system performance. All the discussed strategies have been implemented in real processors, so they are constrained to the available performance counters. Different strategies will be studied according to the characteristics of the running workload. Before discussing each strategy, we will present how performance needs to be characterized, which is crucial when elaborating the strategy. First, we will focus on compute-intensive single-threaded applications where the CPU utilization is saturated (100%) for all the execution time. These strategies pursue to identify symbiotic or complementary applications from a resource consumption perspective. The talk will present a state-of-the-art solution to illustrate these strategies' problems. After that, the talk will focus on multithreaded applications. Unlike the previous ones, these strategies pursue reducing the number of cores used by each application while sustaining the performance or achieving a target performance. State-of-art work strategies will be presented.
More information about this research:https://www.upv.es/pls/oalu/sic_person.Info?p_alias=JSAHUQUI&P_IDIOMA=i
Julio Sahuquillo is a Full Professor at the Universitat Politècnica de València. Among the most relevant recent research lines are those related to real machines. His research work has focused on computer architecture-related topics aimed at improving both the performance and fairness of recent multicore commercial machines. Among these topics are: task to core allocation strategies, cache partitioning, regulation of the prefetcher, and scheduling strategies. The devised approaches have significantly improved the performance of the Linux operating system and the proposals of the state of the art.
On these topics, he has recently given invited talks at the Huawei's Compute and Storage Technology Workshop 2020 (Haifa, Israel), University of Siena (2017, Italy), Murcia (2017, Spain), and a PhD course at the University of Pisa (2018, Italy). He has authored over 200 refereed conference and journal papers. He has received multiple times the best paper award, highlighting the two awards received from the HiPEAC Network of Excellence by the Micro Symposium 2009 and the HPCA 2016 Conference. He has advised 14 PhD theses. During the theses, his students have been awarded the INTEL Doctoral Student Honor Program award, 2013 (35000$);
First Place Graduate Student Research Supercomputing (2013); Computer Science Society of Spain and BBVA Foundation Award in 2017 (5000€); and Outstanding PhD Dissertation Award by IEEE Technical Committee on Scalable Computing (TCSC) in 2017. He is also the co-inventor of an international patent, and the main advisor of the simulator Multi2Sim developed under its direction during the doctoral thesis of R. Ubal, widely used simulator in the scientific community and by companies such as AMD and Nvidia.
During the last 6 years, he has led seven projects funded in more than 200K € each. Regarding technology transfer, he has led three project agreements with leading international companies, all of them aimed at improving the features of distinct components (e.g., processor and memory) of the companies' products. He has also been the Principal Investigator in three competitive national projects that have been funded totally or partially by the Spanish Ministry. He has served as the Principal Investigator of UPV in the ExaNest European project.
