The Versatile Video Coding (VVC) is the most recent image compression standard (H.266) developed and standardised by the Joint Video Experts Team (JVET). It has a compression efficiency of 50% over its predecessor HEVC (H.265). The Encoder of the VVC is very slow and far from being real-time. We have proposed a network-attached FPGA acceleration of the compute intensive tasks of the VVC Encoder. The multi-transform system is a potential compute-intensive task that can be offloaded to the FPGA. The multi-transform system consists of DCT2, DCT8 and DST7 transforms that are used to obtain a two-dimensional transform of the residual image. A transform unit can be of any rectangular shape from 2×2 to 64×64. The hardware architecture proposed consists of two one-D transform units each of which is capable of taking 32pt-transform. In smaller transforms (< 32), multiple lines are transformed in parallel while as in 32pt-transform only one line is transformed at a time. The implementation was targeted to the Intel Arria10 FPGA Board. A maximum of 322 and 1291 frames are transformed per second in 4:2:0 YUV video streams for resolutions 4k and FHD, respectively.
I am Mohd Rafi Lone, a passionate researcher and educator specializing in Signal Processing. With one year of postdoctoral research experience at Fraunhofer HHI in Germany and four years as an Assistant Professor, I have made significant contributions to the field. During my postdoctoral research, my focus was on profiling the versatile video coder (VVC) program to identify compute-intensive operations. By offloading these tasks to FPGAs and utilizing low-latency network attached accelerators, I successfully optimized the video coding process for enhanced performance. As an Assistant Professor, I possess expertise in teaching Analog Electronics, Digital Signal Processing, and VHDL to undergraduate and postgraduate students at the university level. My research, recognized through publications and secured research grants, centers around signal processing algorithms, and their acceleration and optimization for different sets of target devices. Proficient in MATLAB, VHDL, C++, and Python, I have developed many software and hardware solutions for low-memory and resource-constrained visual sensor networks. My dedication lies in advancing in my field and making valuable contributions to academia and research, particularly in FPGA acceleration for signal processing and machine learning algorithms.