The data bandwidth bottleneck in computer systems and ways to deal with it


03.06.2019
Speaker : Prof. Ioannis Sourdis, Chalmers University of Technology
Date : 03.06.2019
Time: 16:10-17:10
Location : "Alkiviades C. Payatakes" Seminar Room, FORTH, Heraklion, Crete
Host : Vassilis Papaefstathiou
Abstract:

Technology allows a large number of cores and accelerators to be integrated on a chip offering potential for higher performance. One of the challenges for getting anywhere close to this performance potential is to be able to supply these processing resources with the large volumes of data required for their computations. New emerging data-intensive applications make the problem even more challenging increasing the need for high data rates. However, the memory bandwidth is pin-limited and power-constrained. In addition, there is significant bandwidth waste in existing on-chip interconnects. In this talk, I will describe a number of techniques for alleviating this data bandwidth bottleneck in current computing systems. First, I will describe our approach for increasing memory bandwidth using hybrid memory systems, composed of 3D-stacked DRAM and conventional off-chip DRAM. Then, I will present our design for aggressive memory compression that aims to utilize memory bandwidth more efficiently. Next, I will show our NoC router architecture which increases the throughput of on-chip interconnects. Finally, (provided there is time left) I will present our dataflow FPGA-based accelerator for emerging stream-processing applications. Besides increasing the effective data bandwidth that reaches the on-chip processing resources, the above techniques also improve latency and energy efficiency.
Bio:

Ioannis (Yiannis) Sourdis is a Professor in Computer Engineering at Chalmers University of Technology, Sweden. He has an engineering diploma Dipl-Eng (2002) and a MSc (2004) in ECE from the TU Crete, Greece, and a PhD (2007) in computer engineering from TU Delft, The Netherlands. His research interests include architecture and design of computer and networking systems, reconfigurable computing, interconnection networks and multiprocessor parallel systems. From 2007 until 2010, Sourdis contributed to the coordination of the HiPEAC Network-of-Excellence (NoE) cluster on Reconfigurable Computing. He holds a patent in an address lookup technique for network routing for which he has received a Dutch STW valorization grant. In 2015, he received an award for co-authoring one of the 25 most significant papers in the FPL conference (during the 25 years history of the conference), that most strongly influenced theory and practice in the field of reconfigurable computing. Sourdis participated in the Pro3, EASY, SARC and HiPEAC FP5 and FP6 European projects; he has coordinated the DeSyRe FP7 project; he participated in the JTI-Artemis EMC2 project as well as in the SHARCS, COSSIM and ECOSCALE Horizon 2020 projects; he also participated in the MEDIAN Cost Action. Moreover, he has received a personal grant from the Swedish research council for the project ScalaNets on Network and Stream processing using reconfigurable computing. Finally, he is member of the HiPEAC NoE, member of IEEE and ACM.