The traditional performance-cost benefits enjoyed for decades from scaling of device area are challenged by two alarming trends: a slowdown of both voltage scaling and frequency increase due to slower scaling of leakage current as compared to area scaling, and a shift to probabilistic design and less reliable silicon primitives due to static and dynamic variations. These lead to a pessimistic projection that it will be impossible to operate all on-chip resources, even at the minimum voltage for safe operation, due to power constraints, and/or the growing design and operational margins used to provide silicon primitives with resiliency against variations will consume the scaling benefits.
Our attempt, presented in this talk, towards reversing these negative Trends is a first-order model that can determine analytically the performance degradation due to permanent faulty cells in prediction arrays. We refer to this degradation as the performance vulnerability factor (PVF). The model can predict, for a given program run, random probability of permanent cell failure, and processor configuration, the expected PVF as well as the PVF probability distribution for an individual or combination of prediction arrays. This facilitates rapid design space exploration of the performance implications of reliability design decisions.
Yiannos Sazeides is an Assistant Professor at the University of Cyprus. He was awarded a PhD from the University of Wisconsin in 1999. He worked in research labs for the development and design of high performance processors with Compaq and Intel. His research interests lie in the area of Computer Architecture with particular emphasis on reliability, memory hierarchy issues, temperature, and analysis of dynamic program behavior.
