Although the dataflow model of execution, with its obvious benefits, has been proposed for a long time, it has not yet been successfully exploited. Nevertheless, as traditional systems have recently started to reach their limits in delivering higher performance, new models of execution that use dataflow-like concepts are being studied.
Among these, Data-Driven Multithreading (DDM) is a multithreading model that effectively hides the communication delay and synchronization overheads. In DDM threads are scheduled as soon as their input data has been produced, i.e. in a dataflow-like way. In addition to presenting a motivation to the dataflow model of execution, this work also presents an overview of the DDM project. In particular it focuses on the Chip Multiprocessor (CMP) implementation using the DDM model, its hardware, runtime system, and performance evaluation.
The Data-Driven Multithreading Chip Multiprocessor (DDM-CMP) inherits the benefits of both the DDM model which allows to overcome the memory wall limitation, and the CMP which offers a simpler design, higher degree of parallelism, and larger power-performance efficiency, therefore overcoming the power wall. Preliminary experimental results show a significant benefit in terms of both speedup and power consumption, making the DDM-CMP architecture an attractive architecture for future processors.
Pedro Trancoso received the undergraduate degree in electrical and computer engineering from Instituto Superior T cnico (IST), Technical University of Lisbon, Lisbon, Portugal, in 1993, the MSc and PhD degrees in computer science from the University of Illinois at Urbana-Champaign, Illinois, U.S.A., in 1995 and 1998. He is currently an Assistant Professor at the Department of Computer Science of the University of Cyprus, Nicosia, Cyprus.
He has worked at IBM T.J. Watson Research Center, U.S.A. as a researcher (1997), at the University of Illinois at Urbana-Champaign, U.S.A. as a visiting scholar (2000), and at Intercollege Limassol, Cyprus as an assistant professor (1998-2001). He has published several papers in the area of computer architecture, with a focus on the memory hierarchy, intelligent memory technologies, architecture-aware optimizations for database workloads and benchmarking, power-performance efficient architectures, multi-core architectures, and the use of graphics processors for general purpose applications.
He was a recipient of a Fulbright scholarship to pursue his PhD studies, an EU-Mobility grant and a HPC-Europa grant to visit, as a researcher, the Supercomputing Center CESCA-CEPBA at the Universitat Politecnica de Catalunya, Barcelona, Spain, in 2002 and 2005.
He is a member of the CoreGrid Network of Excellence, the IEEE and ACM. He has been a member in the Program Committee of several International Conferences including Parallel Architecture and Compilation Techniques, PACT 2004, and Local-Chair of Topic 7 (Parallel Computer Architecture and ILP) of EuroPar 2005. He is currently a member of the Editorial Board for the International Journal of High-Performance System Architecture.
