The increasing levels of integration on modern IC's require comensurate increases on the I/O bandwidth of these ICs. This talk outlines the evolution of signaling and clocking techniques as per pin bandwidths increase from the Mbit to the Gbit range. Particular emphasis is given to contemporary techniques in Clock and Data Recovery as well as Equalization. The talk concludes by describing implementation trade-offs in four contemporary interfaces: Rambus (parallel-memory), SPI4.2 (parallel-datacom), SATA (serial-storage) and XFI (serial-datacom).
(This is an introductory lecture presented as part of a day-long course at the 2004 VLSI Circuits Symposium)
Stefanos Sidiropoulos received his BS and MS in Computer Science from the University of Crete and his PhD in Electrical Engineering from Stanford University in 1997. He has worked in both development and research groups at DEC/WRL, IIT, MIPS and Rambus. Since 2001 he is with Aeluros Inc., a startup company focused on ICs for optical communications. He has been a co-founder of the company, and he is currently the Chief Executive and the Chief Technical Officer. He has been a program committe member of the Intenational Solid State Circuits Conference and a visiting lecturer at Stanford University. His work interests are in mixed signal circuit design, VLSI microarchitectures, CAD and design methodology.
