While the evolution of semiconductor technology has resulted in ever increasing transistor densities, power considerations appear to be limiting our ability to continue increasing clock frequencies at the same pace as in the past. In addition, other key parameters have not kept up with clock frequency. For example, we find ourselves spending more and more resources to address memory latency with limited results.
Finally, increasing design complexity impacts designer productivity and ultimately compromises our ability to keep up with Moore's law. Multicore microprocessor chips appear to provide a temporary reprieve against these limiting factors as along as applications inherently exhibit thread level parallelism and software can be restructured or designed to take advantage of it.
In this talk, we will review the technology trends, explore the motivation behind the recent focus on multicore microprocessor chips, and discuss the key factors that allow such designs to alleviate power and performance constraints. Finally, we will discuss how these trends may impact the evolution of microprocessor design in the long run and point to the critical challenges in this direction.
Yannis Schoinas received his BS and MS from the University of Crete in '89 and '91 respectively. He received his PhD from the University of Wisconsin in '97 building software shared memory systems. Yannis joined Intel immediately thereafter and spent most of his time there working on server platforms. He was a key contributor to the definition of p2p coherence protocols for multiple generations of server platforms. He was also a key contributor to the '07 MP platform architecture where he drove the definition of features such as memory migration and mirroring, system partitioning, configuration management, I/O virtualization and security. Since he transitioned to the Intel Microprocessor Technology Labs 1.5 years ago, he has been focusing on architectural improvements to the OS independent runtime configuration firmware execution environment and on scalability issues associated with the interconnect and cache hierarchy of future multicore designs.
