Jobs

[ICS-2315] Πλήρωση μίας θέσης έκτακτου προσωπικού για «Στελέχη παροχής υπηρεσιών ψηφιακού μετασχηματισμού»
Στο πλαίσιο της υλοποίησης της Πράξης/έργου με τίτλο «European Digital Innovation Hub for Smart Health: Precision Medicine and Innovative E-health Services και ακρωνύμιο «smartHEALTH», η οποία συγχρηματοδοτείται μέσω της Δράσης «Ευρωπαϊκοί Κόμβοι Ψηφιακής Καινοτομίας» του Προγράμματος «Ψηφιακή Ευρώπη 2021-2017» και του Προγράμματος «Ανταγωνιστικότητα 2021-2027» με κωδικό Πράξης ΣΑ (2024ΣΕ16370002), το Ινστιτούτο Πληροφορικής του Ιδρύματος Τεχνολογίας και Έρευνας (ΙΤΕ - ΙΠ) προτίθεται να απασχολήσει έκτακτο προσωπικό για την πλήρωση μίας θέσης για «Στελέχη παροχής υπηρεσιών ψηφιακού μετασχηματισμού» μέσω σύναψης σύμβασης εργασίας ορισμένου χρόνου ιδιωτικού δικαίου.
Laboratory: CeHA
Date of announcement: 28-01-2025
Closing date: 07-02-2025
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[ICS-2312] Call for expression of interest for one (1) BSc holder in Computer Science or Computer Engineering
We seek one experienced member for our team, with a BSc degree in Computer Science or Computer Engineering. The candidate will participate in the R&D activities of FORTH in the context of the project “Craft Understanding, Education, Training, and Preservation for Posterity and Prosperity” (Craeft), funded under Horizon EUROPE, HORIZON-CL2-2021-HERITAGE-01 (RIA). Craeft is coordinated by FORTH-ICS. The project aims to deepen our understanding of making activities that include care, judgement, and dexterity standing on Anthropology, Knowledge Representation, Cognitive Science, Art History, Advanced Digitisation, Audiovisual & Haptic Immersivity, and Computational Intelligence to cover the multifaceted expression of crafts as living and developing heritage, as a sustainable source of income, and as the expression of the mind through imagery, technology, and sedimented knowledge. A generative approach will prove sufficiency for digital conservation, reenactable preservation, and scaling of approach for the full range of materials and techniques. Craeft will catalyse craft education and training with intuitive digital aids, telecommunications, craft-specific simulators, advanced immersivity, and high-end digitisation, to widen access, economise learning, increase exercisability, and relax remoteness constraints in craft learning. The integration of haptics intelligence haptics in digital design connects tacit knowledge in computer-aided craft-specific design tools. Workflow simulation will support experimental archaeology for the recovery of lost techniques. The analytic workflow analysis leads to digital fabrication opportunities for menial tasks, material savings and reuse, and reduction of energy consumption. Digital dimensions attached to individual works of craft will enable certification and attachment of digital content, but also enable reputation and community building, supported by a Community Portal for professionals and the public that connects to the New Media, hosts heterogeneous craft portfolios, and registers practitioner credentials. The efficacy of the approach will be piloted in eight representative craft instances with the cross-cutting objectives of Craft Education & Training, Design, Valorisation, and Community services across the range of materials.
Laboratory: HCI
Date of announcement: 23-01-2025
Closing date: 24-02-2025
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[ICS-2301] Call for expression of interest for one (1) position for an R&D Engineer with a degree in Computer Science or Computer Engineering
We seek one (1) recent graduate Research & Development Engineer with a degree in Computer Science or Computer Engineering for our team. The candidate will contribute to the R&D activities of FORTH in the context of the EC-funded project HIGHER, particularly in (i) development of low-level control firmware and system software, and (ii) validation and evaluation of use cases. The HIGHER project follows the Open Compute Project (OCP) Server family of standards to build processor modules for computation and acceleration, alongside a system security/control module. The project aims to build modular rack-scale systems, running with fully-featured operating systems and runtimes, and incorporating reusable standards-based infrastructure that encompasses hardware, low-level firmware, and systems software, while ensuring trustworthy functionality for managing, securing, and controlling servers. The project's open-source hardware and software outcomes will enhance European Digital Autonomy and facilitate wide adoption. Furthermore, the project will assemble representative software stacks supporting a range of use cases, including accelerated data processing and analysis for converged Cloud and HPC platforms, Infrastructure-as-a-Service with standardized management and monitoring, Platform-as-a-Service facilitating large-scale data processing for ML inference and data analytics, and memory pool management at the server rack level, with access control safeguards aligned with maturing CXL standards.
ΑΠΟΦΑΣΗ ΠΑΡΑΤΑΣΗΣ
Laboratory: CARV
Date of announcement: 16-01-2025
Closing date: 05-02-2025
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[ICS-2242] Πλήρωση μίας (1) θέσης έκτακτου προσωπικού «Διαχείριση έργων έρευνας και ανάπτυξης» μέσω σύναψης σύμβασης εργασίας ιδιωτικού δικαίου ορισμένου χρόνου πλήρους απασχόλησης
Στο πλαίσιο της υλοποίησης της Πράξης α) «Fostering Artificial Intelligence Trust for Humans towards the optimization of trustworthiness through large-scale pilots in critical domains (FAITH)» με κωδικό GA101135932, και β) «Improve Safety in Polymedication by Managing Drug-Drug-Gene Interactions (SafePolyMed) με κωδικό GA 101057639., το Ινστιτούτο Πληροφορικής του Ιδρύματος Τεχνολογίας και Έρευνας (ΙΠ-ΙΤΕ), προτίθεται να απασχολήσει έκτακτο προσωπικό για την πλήρωση μίας θέσης έκτακτου προσωπικού «Διαχείριση έργων έρευνας και ανάπτυξης» μέσω σύναψης σύμβασης εργασίας ιδιωτικού δικαίου ορισμένου χρόνου πλήρους απασχόλησης και αντικείμενο τη διαχείριση έργων έρευνας και ανάπτυξης.
ΑΠΟΦΑΣΗ ΠΑΡΑΤΑΣΗΣ
Laboratory: CBML
Date of announcement: 27-08-2024
Closing date: 20-09-2024
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: 98ΞΙ469ΗΚΥ-Φ1Ρ)
[ICS-2241] Μία (1) θέση έκτακτου προσωπικού για Κάτοχο Μεταπτυχιακού τίτλου σπουδών στο πεδίο της απομόνωσης και σύνθεσης φυσικών προϊόντων με βιολογική δραστικότητα
Αξιολόγηση αποτελεσματικότητας και τοξικότητας χημικών δομών για κλινικές δοκιμές.
Laboratory: ISL
Date of announcement: 26-08-2024
Closing date: 05-09-2024
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: 6ΗΑΕ469ΗΚΥ-Φ97)
[ICS-2240] Call for expression of interest for one (1) position of Hardware R&D Engineer, in the Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH)
We seek one (1) Hardware R&D Engineer for our team. The candidates should have proven experience with hardware design and FPGA prototyping. The candidate will participate in the R&D activities of FORTH-ICS in the context of the H2020-JTI-EuroHPC project The European PILOT. Accelerators provide the majority of performance in modern High-Performance Computing (HPC) systems and are the fundamental building blocks for Exascale systems. The European PILOT (Pilot using Independent Local & Open Technology) will be the first demonstration of two ALL European HPC and High-Performance Data Analytics (HPDA) (AI, ML, DL) accelerators, designed, implemented, manufactured, and owned by Europe. The European PILOT combines open-source software (SW) and open and proprietary hardware (HW) to deliver the first completely European full stack software, accelerator, and integrated ecosystem based on RISC-V accelerators coupled to any general purpose processor (CPU) via PCIe Gen 6.0 or CXL 3.0. This pilot will demonstrate key HPC and HPDA workloads and software stacks. The European PILOT is also the first to demonstrate an ALL European HPC ecosystem. The accelerators will be manufactured in the new European GlobalFoundries 12 nm advanced silicon technology, a major demonstration of European technology independence. The European PILOT combines cutting edge research utilizing SW/HW co-design to demonstrate HPC and HPDA accelerators running key applications and libraries in a full software stack including middleware, runtimes, compilers, and tools for the emerging RISC-V ecosystem. The European PILOT is able to produce a full stack (SW and HW) research prototype by leveraging and extending the work done in multiple European projects like: EPI, MEEP, POP2 CoE, EuroEXA, and ExaNeSt. This pre-production system can only be realized with a combination of existing IP, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the full stack feasibility of the hardware and software. Finally, while the applications we use span AI to HPC, the aggressive ASIC implementation (chiplet size and small geometry) will be the smallest technology node manufactured in Europe and can easily be adapted for a near-future HPC implementation.
Laboratory: CARV
Date of announcement: 23-08-2024
Closing date: 02-09-2024
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: ΨΗ5Ε469ΗΚΥ-ΨΚΝ)
[ICS-2239] Call for expression of interest for one (1) position of Experienced Hardware R&D Engineer, in the Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH)
We seek one (1) Experienced Hardware R&D Engineer for our team. The candidate should have proven multi-year experience on hardware RTL design, integration and validation with a background in European Research Projects. The candidates will participate in the R&D activities of FORTH in the context of the EuroHPC JU project EPI-SGA2. The European Processor Initiative develops a roadmap for future European high-performance low power processors aligned with the EuroHPC roadmap. EPI focuses on processor technologies based on ARM ISA and architecture for covering the short-term needs and HPC accelerator technologies based on RISC-V, the open-source ISA. RISC-V is also candidate to become the Europa’s own technologies for covering long term objectives. SGA2 also seeks to expand the scope of the project into adjacent European and global vertical markets that can leverage HPC to enable new and improved systems and solutions. The EPI SGA2 proposal, built on top of EPI SGA1 represents the second step toward the implementation of this roadmap. SGA2 has a three-year duration with the following objectives: a) Finalize the development and the bring-up of the first generation of low-power processor units developed in SGA1, b) Develop the second generation of the General Purpose Processor (GPP) applying technological enhancements targeting the European Exascale machines with respect to the GPP (Rhea) of SGA1, c) Develop the second generation of low power accelerator test chips, usable by the HPC community for tests and finally d) Develop sound and realistic industrialisation & commercialisation paths and enable the long-term economical sustainability with an industrialization path in the edge computing area, demonstrated in a few well-chosen proof of concepts like autonomous shuttles or video surveillance.
Laboratory: CARV
Date of announcement: 23-08-2024
Closing date: 02-09-2024
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: ΡΦΧΠ469ΗΚΥ-ΤΟ0)
[ICS-2238] Μία (1) θέση έκτακτου προσωπικού για Μηχανικό Λογισμικού με Πτυχίο Ανώτατης Εκπαίδευσης
Εργασίας Ε4.1 Οπτικοποίηση δεδομένων & Ε4.2 Διαδικτυακές Εφαρμογές πρόσβασης Χρηστών και Πίνακες Ελέγχου (Παραδοτέα: Π4.1. Διαδικτυακές Εφαρμογές πρόσβασης Χρηστών).
Laboratory: ICS
Date of announcement: 31-07-2024
Closing date: 22-10-2024
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: ΨΤΒ0469ΗΚΥ-1ΟΑ)

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