Jobs

[ICS-2303] Call for expression of interest for a position of a Research Associate
We seek a member for our team with a background in Information and communication systems. The candidate will participate in the Management and Development activities of FORTH in the context of the project “PATTERN: Planning a Digital Twin for Greener Road Infrastructure, funded under HORIZON-WIDERA-2023-ACCESS-04. The candidate will participate in all aspects of the project with focus to the Pilot Planning, R&D Design and development, IPR. Moreover, the candidate will also assist in the Project Management activities including administrative and technical reporting.
Laboratory: DISCS
Date of announcement: 20-01-2025
Closing date: 03-02-2025
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[ICS-2302] Call for expression of interest for one (1) position of an R&D engineer in Computer Science or Computer Engineering or Electrical Engineering
We seek one (1) R&D Enginner in Computer Science or Computer Engineering or Electrical Engineering. The candidate will participate in the R&D activities of FORTH in the context of the EuroHPC JU-funded project NET4EXA. The NET4EXA project aims to create an advanced interconnect, which will scale to hundreds of thousands of computing nodes and will support modern HPC systems that are designed for massive AI tasks, such as the training of Large Language Models. The interconnect forms the backbone of such systems, and their overall performance is intimately tied to the scalability of the network and its tight coupling with the high-end compute elements.
Laboratory: CARV
Date of announcement: 20-01-2025
Closing date: 30-01-2025
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[ICS-2301] Call for expression of interest for one (1) position for an R&D Engineer with a degree in Computer Science or Computer Engineering
We seek one (1) recent graduate Research & Development Engineer with a degree in Computer Science or Computer Engineering for our team. The candidate will contribute to the R&D activities of FORTH in the context of the EC-funded project HIGHER, particularly in (i) development of low-level control firmware and system software, and (ii) validation and evaluation of use cases. The HIGHER project follows the Open Compute Project (OCP) Server family of standards to build processor modules for computation and acceleration, alongside a system security/control module. The project aims to build modular rack-scale systems, running with fully-featured operating systems and runtimes, and incorporating reusable standards-based infrastructure that encompasses hardware, low-level firmware, and systems software, while ensuring trustworthy functionality for managing, securing, and controlling servers. The project's open-source hardware and software outcomes will enhance European Digital Autonomy and facilitate wide adoption. Furthermore, the project will assemble representative software stacks supporting a range of use cases, including accelerated data processing and analysis for converged Cloud and HPC platforms, Infrastructure-as-a-Service with standardized management and monitoring, Platform-as-a-Service facilitating large-scale data processing for ML inference and data analytics, and memory pool management at the server rack level, with access control safeguards aligned with maturing CXL standards.
Laboratory: CARV
Date of announcement: 16-01-2025
Closing date: 27-01-2025
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[ICS-2272] ICS Director
Announcement for the position of Director, Institute of Computer Science (in greek only)
Date of announcement: 06-11-2024
Closing date: 20-01-2025
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Archive

[ICS-1741] Μία (1) θέση έκτακτου προσωπικού για Κάτοχο Μεταπτυχιακού τίτλου σπουδών στην Πληροφορική
Σχεδίαση, ανάπτυξη και έλεγχο του Μητρώου και Εφαρμογής Καταγραφής Νευροεκφυλιστικών Νοσημάτων και Πρόδρομων Μορφών τους και Αποθετηρίου Γονιδιακών Δεδομένων.
Laboratory: ISL
Date of announcement: 22-06-2021
Closing date: 07-07-2021
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: ΨΤ6Ρ469ΗΚΥ-2ΒΚ)
[ICS-1740] Call for expression of interest for one (1) BSc holder in Computer Science in the Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH)
We seek one member for our team at the graduate level, with a degree in Computer Science. The candidate will participate in the R&D activities of FORTH in the context of the project “COllaborative Platform for trAnsmedia storytelling and cross channel distribution of EUROPEan sport events” (COPA EUROPE), funded under Horizon 2020, ICT‐44‐2020 ‐ Next Generation Media. COPA EUROPE is coordinated by Worldline Iberia and FORTH‐ICS is a member of the project consortium. The project aims to address the exploding demand for non‐linear sports consumption (live and eSports) by leveraging Over The Top streaming and combining it with new set of media technologies that will democratise the consumer experience, enable cost‐sensitive live video from anywhere, and personalize the distribution to change the experience of each viewer individually. COPA EUROPE will deliver a cloud‐based infrastructure for harvesting, accommodating, transmitting and distributing digital media with regard to sport and competitive events, including the infrastructure needed to allow content creators and producers of live coverage to react to live outcomes, via innovative workflows.
Laboratory: HCI
Date of announcement: 18-06-2021
Closing date: 06-07-2021
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: Ψ6ΧΒ469ΗΚΥ-6ΕΩ)
[ICS-1739] Call for expression of interest for one (1) position of Hardware Design and Test Engineer, in the Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH)
We seek one (1) Hardware Design and Test Engineer for our team, with background in European Research Projects. The candidate will participate in the R&D activities of FORTH in the context of the EuroHPC JU project eProcessor. The eProcessor project combines open source software (SW)/hardware (HW) to deliver the first completely open source European full stack ecosystem based on a new RISC‐V CPU coupled to multiple diverse accelerators that target traditional HPC and extend into mixed precision workloads for High Performance Data Analytics (HPDA), (AI, ML, DL and Bioinformatics). eProcessor will be extendable (open source), energy‐efficient (low power), extreme‐scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on‐chip and/or off‐chip components).
Laboratory: CARV
Date of announcement: 18-06-2021
Closing date: 06-07-2021
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: 65Κ5469ΗΚΥ-Ω56)
[ICS-1738] Call for expression of interest for one (1) position of an Experienced RTL Design and Test Engineer, in the Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH)
We seek one (1) Experienced RTL Design and Test Engineer for our team. The candidate should have proven experience on hardware RTL design, integration and validation with a background in European Research Projects. The candidate will participate in the R&D activities of FORTH in the context of the EuroHPC JU project eProcessor. The eProcessor project combines open source software (SW)/hardware (HW) to deliver the first completely open source European full stack ecosystem based on a new RISC‐V CPU coupled to multiple diverse accelerators that target traditional HPC and extend into mixed precision workloads for High Performance Data Analytics (HPDA), (AI, ML, DL and Bioinformatics). eProcessor will be extendable (open source), energy‐efficient (low power), extreme‐scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on‐chip and/or off‐chip components).
Laboratory: CARV
Date of announcement: 18-06-2021
Closing date: 06-07-2021
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DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: Ρ7Ω7469ΗΚΥ-Ψ76)
[ICS-1737] Call for expression of interest for one (1) position of an Engineer of Computer Science or Engineering Department, in the Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH)
We seek one Hardware & RTL Design and FPGA engineer for our team. The candidate will participate in the R&D activities of FORTH in the context of the project RED‐SEA: “Network Solution for Exascale Architectures”. The EuroHPC Research & Innovation project RED‐SEA started in April 2021 and will last for 3 years. The next generation of Exascale systems will critically require an efficient network, that will support massively parallel processing systems (hundreds of thousands of nodes, millions of cores), provide a set of features allowing applications to scale efficiently at Exascale level and beyond, be prepared for power‐efficient accelerators and compute units, and support wide‐spread and emerging datacentric and AI‐related applications. The RED‐SEA consortium pursues this target, leveraging key European competences & background, including BXI, the key production‐proven European Interconnect, as well as results from a number of EU‐funded projects on interconnects and HPC systems.
Laboratory: CARV
Date of announcement: 18-06-2021
Closing date: 06-07-2021
More info (english version)
Available Results :
Results
DIAVGEIA Search Number: (https://diavgeia.gov.gr with ADA: Ψ0ΓΡ469ΗΚΥ-ΡΘ3)

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