• G. Passas, M. Katevenis, D. Pnevmatikatos: "Crossbar NoCs Are Scalable Beyond 100 Nodes", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ISSN: 0278-0070, vol. 31, issue 4, April 2012, pp. 573-585; DOI: 10.1109/TCAD.2011.2176730
• G. Passas, M. Katevenis, D. Pnevmatikatos: "VLSI Micro-Architectures for High-Radix Crossbar Schedulers", Proc. of the 5th ACM/IEEE Int. Symposium on Networks-on-Chips (NOCS 2011), ISBN 978-1-4503-0720-8, Pittsburgh, PA, USA, 1-4 May 2011, 8 pages.
• - Preprint in PDF (200 KBytes) - © Copyright 2011 by ACM.
  - Presentation Slides in PDF (360 KBytes) - © Copyright 2011 by FORTH.
• G. Passas, M. Katevenis, D. Pnevmatikatos: "A 128x128x24Gb/s Crossbar, Interconnecting 128 Tiles in a Single Hop, and Occupying 6% of their Area", Proc. of the 4th ACM/IEEE Int. Symposium on Networks-on-Chips (NOCS 2010), Grenoble, France, 3-6 May 2010, pp. 87-95, doi: 10.1109/NOCS.2010.37; IEEE Computer Society ISBN 978-0-7695-4049-8.
  - Preprint in PDF (70 KBytes) - © Copyright 2010 by ACM/IEEE.
  - Presentation Slides in PDF (210 KBytes) - © Copyright 2010 by FORTH.
• G. Michelogiannakis, D. Pnevmatikatos, M. Katevenis: "Approaching Ideal NoC Latency with Pre-Configured Routes", Proc. 1st ACM/IEEE Int. Symposium on Networks-on-Chips (NOCS'07), Princeton, NJ, USA, 7-9 May 2007;
  - Preprint of March 2007 in PDF (130 KBytes) or PS (400 KBytes); 10 pages - © Copyright 2007 by IEEE.
  - Presentation Slides in PDF (400 KBytes) - © Copyright 2007 by FORTH.
  

Other past work in Packet Switch Architecture:

• Buffered Crossbar (CICQ), Variable-Size Packet Switching.
• Benes Fabrics with Internal Backpressure for Scalable Non-Blocking Switching.
• Multi-Lane Architectures for Robust and Secure Communication Networks.
• Weighted-Round-Robin Scheduling:
  • Fast Parallel Comparator Tree for Minimum finding.
  • Pipelined Heap (Priority Queue) Management.
  • WRR Scheduler using Per-Class Urgency Counters.
• Per-Flow Queueing.
• Flow Control: ATLAS I: 10 Gb/s single-chip ATM switch with backpressure (1995-99).
• Wormhole IP over ATM.
• Pipelined Memory Shared Buffer for VLSI Switches.
• Packet Switch Architecture: another list, similar to this one, of past projects in this area in FORTH-ICS-CARV.

© Copyright 2007-2012 by FORTH or the IEEE:
These papers are protected by copyright. Permission to make digital/hard copies of all or part of this material without fee is granted provided that the copies are made for personal use, they are not made or distributed for profit or commercial advantage, the FORTH or IEEE copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of the Foundation for Research & Technology - Hellas (FORTH) or the IEEE. To copy otherwise, in whole or in part, to republish, to post on servers, or to redistribute to lists, requires prior specific written permission and/or a fee.

Up to CARV-ICS-FORTH Last updated: Apr. 2012, by M. Katevenis.