Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

ASPIDA DLX Processor

The ASPIDA open-source DLX supports the full DLX integer ISA. Floating point operations are not supported in the current version of the processor, and may be added as part of the exploitation plan of the ASPIDA project. The ASPIDA DLX contains two memory interfaces, following the original DLX model, which support byte, half-word and word transfers. Branches follow the conventional RISC semantics and require a branch delay slot, i.e. the instruction followed by the branch is always executed. A vectored interrupt co-processor, including an interrupt cause register and an exception program counter, is included.

The ASPIDA DLX supports the three operation types of the DLX ISA:

I-type: logic/arithmetic operations performed between a register and an immediate value. Conditional branches are also I-type instructions.
R-type: logic/arithmetic operations performed between two registers. Load and store instructions are also R-type instructions.
J-type: jump and jump-and-link instructions

The instruction layout for each instruction type is shown in the figure below.

The integer subset of the DLX ISA is shown in the figures below. Supported instructions are ticked in the tables.