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Asynchronous Circuit and System Design Group | ||
Asynchronous Open-Source DLX Processor (ASPIDA)
In our implementation we de-synchronize the DLX. The global clock is removed and is replaced by handshaking controllers. The flip-flops are replaced by pairs latches. The figure below shows the datapath of the de-synchronized DLX. As you can see, the latches that separate the datapath stages are locally clocked by controllers, which are responsible for producing the appropriate signals so that the data move safely from one pipeline stage to the next.  |
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