Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

ASPIDA DLX Processor Architecture

The DLX is a 32-bit 5-stage pipelined RISC CPU architecture. A detailed diagram of the pipeline stages of the architecture is shown below.

The pipeline stages of the DLX architecture operate as follows:

Instruction Fetch(IF):     The next instruction to be executed is read from the instruction memory at the address pointed by the
                                        Program Counter(PC) register. The next address is computed as the current address plus 4 or the value
                                        coming from the next stage if a jump has to be executed.

Instruction Decode(ID): The instruction coming from the IF stage is decoded and the register file is accessed. Conditional branches
                                        are also evaluated in this stage and the jump address is computed and sent back to the IF stage.

Execute (EX):                Logic and arithmetic operations are executed on the operand coming from the ID stage. The result of this
                                        operation can either be a value to be written back in the register file or the address of the data memory to
                                        be accessed in the next stage.

Memory(MEM):            Data memory is accessed (either read or write).

Write Back(WB):            The value to be written in the register file (if any) is sent back to the ID stage.