module pulse_delay(inp, outp,outp1);

input inp;
output outp;
output outp1;
wire outp1;

wire wint1, wint2, wint3, wint4, wint5, wint6, wint7, wint8, wint9;

// synthesis attribute KEEP of wint1 is TRUE
not pda1 (wint1, inp);

// synthesis attribute KEEP of outp is TRUE
not pda14 (outp, wint1);
//synthesis attribute keep of outp1 is true
and and1 (outp1,outp,outp);

endmodule