module matched_delay(inp2, inp3, outp2, delay_select);

input inp2;
input inp3;
input [1:0] delay_select;
output outp2;

wire outp2;

wire wint1, wint2, wint3, wint4, wint5, wint6, wint7, wint8, wint9, wint10;
wire wint11, wint12, wint13, wint14, wint15, wint16, wint17, wint18, wint19, wint20;
wire wint21, wint22, wint23, wint24, wint25, wint26, wint27, wint28, wint29, wint30;
wire IF_delay_el1, IF_delay_el2, IF_delay_el3, IF_delay_el4;
// ##synthesis attribute KEEP of inp2 is TRUE
// synthesis attribute KEEP of wint1 is TRUE
myand mda1 (wint1, inp2, inp3);
// synthesis attribute KEEP of wint2 is TRUE
myand mda2 (wint2, inp2, wint1);
// synthesis attribute KEEP of wint3 is TRUE
myand mda3 (wint3, inp2, wint2);
// synthesis attribute KEEP of wint4 is TRUE
myand mda4 (wint4, inp2, wint3);
// synthesis attribute KEEP of wint5 is TRUE
myand mda5 (wint5, inp2, wint4);
// synthesis attribute KEEP of wint6 is TRUE
myand mda6 (wint6, inp2, wint5);
// synthesis attribute KEEP of wint7 is TRUE
myand mda7 (wint7, inp2, wint6);
// synthesis attribute KEEP of wint8 is TRUE
myand mda8 (wint8, inp2, wint7);
// synthesis attribute KEEP of wint9 is TRUE
myand mda9 (wint9, inp2, wint8);
// synthesis attribute KEEP of wint10 is TRUE
myand mda10 (wint10, inp2, wint9);
// synthesis attribute KEEP of wint11 is TRUE
myand mda11 (wint11, inp2, wint10);
// synthesis attribute KEEP of wint12 is TRUE
myand mda12 (wint12, inp2, wint11);
// synthesis attribute KEEP of wint13 is TRUE
myand mda13 (wint13, inp2, wint12);
// synthesis attribute KEEP of wint14 is TRUE
myand mda14 (wint14, inp2, wint13);
// synthesis attribute KEEP of wint15 is TRUE
myand mda15 (wint15, inp2, wint14);
// synthesis attribute KEEP of wint16 is TRUE
myand mda16 (wint16, inp2, wint15);
// synthesis attribute KEEP of wint17 is TRUE
myand mda17 (wint17, inp2, wint16);
// synthesis attribute KEEP of wint18 is TRUE
myand mda18 (wint18, inp2 , wint17);
// synthesis attribute KEEP of wint19 is TRUE
myand mda19 (wint19, inp2, wint18);
// synthesis attribute KEEP of wint20 is TRUE
myand mda20 (wint20, inp2, wint19);
// synthesis attribute KEEP of wint21 is TRUE
myand mda21 (wint21 , inp2, wint20);
// synthesis attribute KEEP of wint22 is TRUE
myand mda22 (wint22, inp2 , wint21);
// synthesis attribute KEEP of wint23 is TRUE
myand mda23 (wint23, inp2 , wint22);
// synthesis attribute KEEP of wint24 is TRUE
myand mda24 (wint24, inp2 , wint23);
// synthesis attribute KEEP of wint25 is TRUE
myand mda25 (wint25, inp2 , wint24);
// synthesis attribute KEEP of wint26 is TRUE
myand mda26 (wint26, inp2 , wint25);
// synthesis attribute KEEP of wint27 is TRUE
myand mda27 (wint27, inp2, wint26);
// synthesis attribute KEEP of wint28 is TRUE
myand mda28 (wint28, inp2 , wint27);
// synthesis attribute KEEP of wint29 is TRUE
myand mda29 (wint29, inp2, wint28);
// synthesis attribute KEEP of wint30 is TRUE
myand mda30 (wint30, inp2, wint29);
// synthesis attribute KEEP of wint31 is TRUE
myand mda31 (wint31, inp2, wint30);
// synthesis attribute KEEP of wint32 is TRUE
myand mda32 (wint32 , inp2, wint31);
// synthesis attribute KEEP of wint33 is TRUE
myand mda33 (wint33, inp2 , wint32);
// synthesis attribute KEEP of wint34 is TRUE
myand mda34 (wint34, inp2 , wint33);
// synthesis attribute KEEP of wint35 is TRUE
myand mda35 (wint35, inp2 , wint34);
// synthesis attribute KEEP of wint36 is TRUE
myand mda36 (wint36, inp2 , wint35);
// synthesis attribute KEEP of wint37 is TRUE
myand mda37 (wint37, inp2 , wint36);
// synthesis attribute KEEP of wint38 is TRUE
myand mda38 (wint38, inp2, wint37);
// synthesis attribute KEEP of wint39 is TRUE
myand mda39 (wint39, inp2 , wint38);
// synthesis attribute KEEP of wint40 is TRUE
myand mda40 (wint40, inp2, wint39);

// synthesis attribute KEEP of outp2 is TRUE   
// synthesis attribute KEEP of IF_delay_el1 is TRUE
// synthesis attribute KEEP of IF_delay_el2 is TRUE
// synthesis attribute KEEP of IF_delay_el3 is TRUE
// synthesis attribute KEEP of IF_delay_el4 is TRUE

assign IF_delay_el1 = wint26;
assign IF_delay_el2 = wint30;
assign IF_delay_el3 = wint34;
assign IF_delay_el4 = wint40;
assign outp2 = delay_select == 'b00 ? IF_delay_el1  :
           delay_select == 'b01 ? IF_delay_el2  :
           delay_select == 'b10 ? IF_delay_el3  :
           delay_select == 'b11 ? IF_delay_el4  : IF_delay_el4;

endmodule