Asynchronous Circuits & Systems (2001 - 2010)


Asynchronous Open-Source DLX Processor (ASPIDA)

ASPIDA was an EU-funded Demonstration project, which aimed at demonstrating the industrial viability and IP Reuse potential of asynchronous parts by delivering a free, open-source, industrial-quality, asynchronous IP Processor Core, designed, tested and implemented using industrial EDA tools, which will support Open IP Reuse specifications, so it can be easily embedded into any Open IP System-On-a-Chip. The architecture executes the DLX instruction set, a well-known and well-supported generic RISC architecture designed for educational and research purposes. Inspired from the success of open-source software, this project aims to efficiently tackle the drawbacks of IP Reuse by promoting free, open-source hardware.

ASPIDA was a joint effort of FORTH-ICS, Politecnico di Torino, Manchester University and IHP Microelectronics.

The asynchronous DLX processor has been successfully implemented both in ASIC and FPGA versions.

ASIC version

FPGA version

 

 

A comprehensive FAQ about ASPIDA is provided here. See also our demo for the ASYNC 2004 conference!

The ASPIDA FAQ and files are also available as an Opencores project.

Asynchronous Design using Commercial EDA Tools (ASIC or FPGA)

The use of commercial EDA tools, ASIC or FPGA, for the implementation of asynchronous circuits and systems was an R&D activity included in the ASPIDA project and afterwards. If asynchronous circuits are to be considered for broad adoption by industry, the transition from synchronous to asynchronous must occur smoothly and by exploiting existing EDA technology and know-how instead of advocating a radical, instant change in design practices. The aim of this research was to focus on using commecial, industrial tools for asynchronous design and demonstrating that this is indeed possible. To achieve this goal it is often necessary to exploit specific features of these tools, including scripting, or develop help applications, which are incorporated in the design flow.

Asynchronous SoC Interconnects

System-on-Chip (SoC) interconnect has often been quoted as a very suitable application for asynchronous design. Being able to transmit data across IP blocks at non-multiples of clock cycles, without the need for clock domain synchronization and the problem of clock skew is a very good solution to the problem of large-scale SOC design. Our research on asynchronous interconnects was concerned with identifying potential approaches for asynchronous SOC interconnects and both implement and evaluate these approaches using physical modeling techniques.

Asynchronous Design for Variability and High-performance

This research area aimed at demonstrating that asynchronous circuits can indeed exhibit better variability and higher-performance compared to their synchronous counterparts. Dual-rail or multi-rail logic implements asynchronous circuits with completion-detection. It has been shown by previous work that completion-detection alone is in most cases not sufficient for achieving better performance compared to that of a synchronous system. This work exploited techniques based on completion-detection that can indeed improve performance or enable better control of circuit variability.

Study of Bursting and Event Spacing Phenomena in Asynchronous Handshaking Structures

Asynchronous intercommunicating structures (e.g. rings) can exhibit bursting or event spacing phenomena as has been shown in the literature. This research aimed at furthering the understanding of such phenomena, depending on the type of asynchronous circuits used, being able to control them and reason about them.

 


Asynchronous Systems Background

Asynchronous design is not new. Asynchronous design methods date back to the 1950's. However, the clock signal, which is traditionally used by circuit designers, in order to enforce global timing to a digital circuit, has historically been considered as an essential device. The following is a famous quote by Alan Turing who considered the clock signal as necessary for the operation of a digital computer and claimed that asynchronous circuits are hard to design:

"We might say that the clock enables us to introduce a discreteness into time, so that time for some purposes can be regarded as a succession of instants instead of a continuous flow. A digital machine must essentially deal with discrete objects, and in the case of ACE this is made possible by the use of the clock. All other computing machines except for human and other brains that I know of do the same. One can think up ways of avoiding it, but they are very awkward..."

More than 60 years later, asynchronous design has experienced important breakthroughs both in design methods and approaches and practical demonstrator designs from both academia and industry.

Advantages of Asynchronous Design

  • Elimination of clock tree related problems (clock skew and clock power)
    As digital systems become larger, an increasing amount of effort has been placed to enforce the global timing model, with significant effort being paid to guarantee that clock skew and even clock power are kept under control. In asynchronous systems, skew can be tolerated and power is well controlled.

  • Average-case performance
    In synchronous design, cycle time and performance are dictated by worst-case conditions, as clock period is set to be long enough to accomodate the slowest possible data propagation. Asynchronous circuits can change their speed dynamically and their performance is data-driven and governed by average-case delay.

  • Adaptability to processing and environmental variations
    The delay of a VLSI circuit varies significantly over processing runs, supply voltages and operating conditions. Synchronous circuit have a fixed clock rate set according to some allowed degree of variations. Asynchronous circuits are adaptive and can operate correctly under all variations with their speed increasing or descreasing, as is necessary.

  • Modularity and re-use
    Asynchronous components have plug-and-play capabilities because of the absence of global timing assumptions.

  • Lower power and lower Electromagnetic Emissions
    Asynchronous circuits reduce synchronisation power and automatically power-down unused components; asynchronous circuits are also quiet as they avoid unneeded signal transitions and spread out needed signal transitions.


Publications

Papers in Proceedings

  • Andrikos, N., Lavagno, L., Pandini, D., & Sotiriou, Ch.P. (2007). A fully-automated desynchronization flow for synchronous circuits. 2007 44th ACM/IEEE Design Automation Conference, DAC"07. 4 June 2007 through 8 June 2007, San Diego, CA. (pp. 982-985)

  • Kassapaki, E., Mattheakis, P.M., & Sotiriou, Ch.P. (2006). Actual-delay circuits on FPGA: Trading-off LUTs for speed. 2006 International Conference on Field Programmable Logic and Applications, FPL. 28 August 2006 through 30 August 2006, Madrid. (pp. 599-604)

  • Zebilis, V., & Sotiriou, Ch.P. (2005). Controlling event spacing in self-timed rings. In Proceedings of the 11th IEEE International Conference on Asynchronous Circuits and Systems (ASYNC)14-16 March, New York, USA. (pp. 109)

  • Efthymiou, A., Sotiriou, Ch.P., & Edwards, D. (2004). Automatic scan insertion and pattern generation for asynchronous circuits. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 0416 February 2004 through 20 February 2004, Paris. (pp. 672-673)

  • Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2004). Coping with the variability of combinational logic delays. Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on. October, San Jose, USA. (pp. 505-508)

  • Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., & Sotiriou, Ch.P. (2004). From synchronous to asynchronous: An automatic approach. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 0416 February 2004 through 20 February 2004, Paris. (pp. 1368-1369)

  • Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2003). A Concurrent Model for De-Synchronization. In Proceedings of the 12th International Workshop on Logic and Synthesis (IWLS)May

  • Amde, M., Blunno, I., & Sotiriou, Ch.P. (2003). Automating the design of an asynchronous DLX microprocessor. Proceedings of the 40th Design Automation Conference. 2 June 2003 through 6 June 2003, Anaheim, CA. (pp. 502-507)

  • Sotiriou, Ch.P., & Lavagno, L. (2003). De-synchronization: asynchronous circuits from synchronous specifications. SOC Conference, 2003. Proceedings. IEEE International, 17-20 September, Portland, Oregon. (pp. 165)

  • Sotiriou, Ch.P. (2002). Implementing asynchronous circuits using a conventional EDA tool-flow. In Proceedings of the 39th Design Automation Conference (DAC). June, (pp. 415-418)

  • Sotiriou, Ch.P. (2001). Direct-mapped asynchronous finite-state machines in CMOS technology. ASIC/SOC Conference, 2001. In Proceedings of the 14th International ASIC/SOC ConferenceSeptember, Arlington, VA, USA. (pp. 105-109)

Journal Articles
  • Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2006). Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 25 (10), (1904-1921), (0278-0070)

  • Dobkin, R., Ginosar, R., & Sotiriou, Ch.P. (2006). High rate data synchronization in GALS SoCsIEEE Trans Very Large Scale Integr VLSI Syst. 14 (10), (1063-1074), (10638210)

  • Dobkin, R., Ginosar, R., & Sotiriou, Ch.P. (2004). Data synchronization issues in GALS SoCsProc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst.. 10, (170-179), (15228681)

  • Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., & Sotiriou, Ch.P. (2004). Handshake protocols for de-synchronization. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst.. 10, (149-158), (15228681)

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